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ISL29003
Register Set
There are eight registers that are available in the ISL29012. Table 1 summarizes the available registers and their functions.
TABLE 1. REGISTER SET
BIT
ADDR
00h
01h
02h
REG NAME
COMMAND
CONTROL
Interrupt
7
ADCE
0
ITH_HI7
6
ADCPD
0
ITH_HI6
5
TIMM
INT_FLAG
ITH_HI5
4
0
0
ITH_HI4
3
ADCM1
GAIN1
ITH_HI3
2
ADCM0
GAIN0
ITH_HI2
1
RES1
IC1
ITH_HI1
0
RES0
IC0
ITH_HI0
DEFAULT
00h
00h
FFh
Threshold_HI
03h
Interrupt
ITH_LO7
ITH_LO6
ITH_LO5
ITH_LO4
ITH_LO3
ITH_LO2
ITH_LO1
ITH_LO0
00h
Threshold_LO
04h
05h
LSB SENSOR
MSB
S7
S15
S6
S14
S5
S13
S4
S12
S3
S11
S2
S10
S1
S9
S0
S8
00h
00h
SENSOR
06h
07h
LSB TIMER
MSB TIMER
T7
T15
T6
T14
T5
T13
T4
T12
T3
T11
T2
T10
T1
T9
T0
T8
00h
00h
TABLE 2. WRITE ONLY REGISTERS
TABLE 5. TIMING MODE
REGISTER
FUNCTIONS/
BIT 5
OPERATION
ADDRESS
b1xxx_xxxx
NAME
sync_I 2 C
DESCRIPTION
Writing a logic 1 to this address bit ends the
current ADC-integration and starts another.
Used only with External Timing Mode.
0
1
Internal Timing Mode. Integration time is internally timed
determined by f OSC , R EXT , and number of clock cycles.
External Timing Mode. Integration time is externally
timed by the I 2 C host.
bx1xx_xxxx
clar_int
Writing a logic 1 to this address bit clears
the interrupt.
4. Photodiode Select Mode; Bits 3 and 2. Setting Bit 3 and
Command Register 00(hex)
The Read/Write command register has five functions:
Bit 2 to 1 and 0 enables ADC to give light count DATA
output.
TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3
1. Enable; Bit 7. This function either resets the ADC or enables
the ADC in normal operation. A logic 0 disables ADC to
reset-mode. A logic 1 enables ADC to normal operation.
TABLE 3. ENABLE
BITS 3:2
0:0
0:1
1:0
MODE
Disable ADC
Disable ADC
Light count DATA output in signed (n-1) bit *
BIT 7
0
OPERATION
Disable ADC-core to reset-mode (default)
1:1
No operation.
1
Enable ADC-core to normal operation
* n = 4, 8, 12,16 depending on the number of clock cycles
function.
2. ADCPD; Bit 6. This function puts the device in a
power-down mode. A logic 0 puts the device in normal
operation. A logic 1 powers down the device.
TABLE 4. ADCPD
5. Width; Bits 1 and 0. This function determines the number
of clock cycles per conversion. Changing the number of
clock cycles does more than just change the resolution of
the device. It also changes the integration time, which is
BIT 6
OPERATION
the period the device’s analog-to-digital (A/D) converter
0
1
Normal operation (default)
Power Down
.
samples the photodiode current signal for a lux
measurement.
TABLE 7. WIDTH
3. Timing Mode; Bit 5. This function determines whether the
integration time is done internally or externally. In Internal
Timing Mode, integration time is determined by an
internal dual speed oscillator (f OSC ), and the n-bit (n = 4,
8, 12,16) counter inside the ADC. In External Timing
Mode, integration time is determined by the time between
three consecutive external-sync sync_ I 2 C pulses
commands.
5
BITS 1:0
0:0
0:1
1:0
1:1
NUMBER OF CLOCK CYCLES
2 16 = 65,536
2 12 = 4,096
2 8 = 256
2 4 = 16
FN6476.2
November 17, 2011
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